David BALDWIN <PICLIST@MITVMA.MIT.EDU> wrote:

>         clrf temp
> loop    set WREN bit
>         write 55h to EECON2
>         write AAh to EECON2
>         set WR bit
>         move temp --> EEADR
>         set WR bit
>         btfss temp,6
>         goto loop

David:

The proper sequence is:

        clear TEMP

    LOOP:

        copy TEMP to EEADR
        (optionally load EEDATA with something here)

        set WREN
        write 55 to EECON2
        write AA to EECON2
        set WR

        wait for WR to clear

        increment TEMP
        btfss TEMP,6
        goto LOOP

Your code only wrote to address 63 because you failed to wait for
the WR bit to clear (which signals the end of the internal write
cycle).

-Andy

=== Andrew Warren - fastfwd@ix.netcom.com
=== Fast Forward Engineering - Vista, California
===
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