John Payson <supercat@MCS.NET> wrote:
> Right.  What happens if FSR happens to be pointing at a register which
> would be affected by the read?

and later added:
> Well, on the 16C74, a RETURN instruction (0x000D) does a read to port D (at
> address 0x000D) which will clear the incoming byte flag if that port is
> used in parallel-slave mode.

Wolfram Liebchen <liebchen@FFO.FGAN.DE> wrote:
> I can't believe, that PICs behave the way you say.
> It should be easy, to decode special instructions in a way that they don't
> have theses side effects you mentioned.
> The data sheets _SHOULD_ also mention them?!?

Yes, they should.  But they don't.

Another example of this is the CLRW instructions, which is described in the
data sheets as having the bit pattern 00 0001 0xxx xxxx, where the "x"s are
"don't care".

Originally the Microchip assemblers set all of the don't care bits to 0,
but if the FSR points to a register which has a side effect when read,
this coding will cause problems.  This is understandable since CLRW is really
just a ",W" variant of the CLRF instruction.

Recent versions of MPASM now use 00 0001 0000 0011 for CLRW, so the
superfluous read is to the PCL register, and has no side effect.  As far as I
know, the PIC data sheets have not been updated to reflect this.

It would appear that all the instructions in the range 0000h..0fffh hex
do a read, even the "special" instructions from 0000h..007fh:

        NOP     00 0000 0xx0 0000       (it appears that they have
                                        special-cased 0000h to not read IND,
                                        but I'm not sure about 0020h, 0040h,
                                        and 0060h)
        RETURN  00 0000 0000 1000       reads PORTD, TRISD, PORTG, TRISG,
                                        ADCON0, ADCON1, EEDATA, EECON1, or
                                        unimplemented, depending on the part
                                        and the RP0/RP1 bank switch bits
        RETFIE  00 0000 0000 1001       reads PORTE, TRISE, ADRES, EEADDR,
                                        EECON2, or unimplemented

The following instructions no doubt do an extraneous read also, but of
locations from 62h to 67h that are likely to always either be RAM or
unimplemented:

        OPTION          00 0000 0110 0010       (obsolete)
        SLEEP           00 0000 0110 0011
        CLRWDT          00 0000 0110 0100
        TRIS    PORTA   00 0000 0110 0101       (obsolete)
        TRIS    PORTB   00 0000 0110 0110       (obsolete)
        TRIS    PORTC   00 0000 0110 0111       (obsolete)

Eric