> I told a lie;
>
> > Here's a tricky one; the 68000 has two forms of relative branch; one
> > If you write
> >
> >         jmp     next
> > next:
> >
> > then you get a four byte instruction!
>
> Depending on the assembler, you may well get a 2 byte instruction -
> it has the same bit pattern as NOP.

The opcode for NOP on the 68000 is decidedly NOT the same as the opcode for
a jump-short to the next instruction.  On the 68000, a jump instruction has
an eight bit relative address.  If this field is non-zero, it will be added
to the address of the following instruction and loaded into the PC.  If this
field is zero, then the 68000 will fetch the next 16 bits and use those as a
relative address.  I am not sure why the designers at Motorola did not shift
the 8-bit displacement left a bit (since all addresses have to be even) but
nonetheless the crucial point remains that on the 68000 it is not possible to
have a short jump to the next instruction and any compiler or assembler which
outputs such a thing is broken.

This does open up the interesting question of what an assembler should actually
do upon encountering a "branch to next instruction" within the code.  There are
three options that I can see:

[1] Output some useless one-word instruction [e.g. NOP].  This will be compact
    but it will produce slightly skewed timings.

[2] Output a short jump ahead 2, followed by a NOP.  The NOP will put the tar-
    get of the jump in an acceptable place, while giving execution timings
    comparable to just using a short jump (if such a thing were possible).  The
    extra NOP may mess up cache timings, however.

[3] Output a long jump to next instruction.  This may be slower to execute than
    method #2, and probably doesn't have any particular advantage, but it is
    the only output which is "literally" correct.