> Steve Hardy asked:
>
> >Gregg stated a Rds(on) coefficient of +0.6%/K hovever said reference
 indicated
> >only +0.1%/K.
>
> It was only yesterday, but of course I can't find the book I referenced, to
> double check.  Anyhow, the figure quoted was per degree Celcius, not Kelvin
> which Steves text seems to specify.

As a previous writer stated, deg C and K are the same interval.  Note that
the correct terminology is 'Kelvin' not 'degree Kelvin'.  [I feel kinda
sorry for the non-metric countries which have to grapple with Fahrenheit
and (God forbid) Rankine.]

>
> >Never mind, but I would be interested in knowing the tempco
> >of the threshold voltage since this is not mentioned,
>
> A quick check at some MOSFET devices in a Motorola data book seems to show a
> fairly consistent and linear negative 0.6 to 0.7 % /degree C tempco for the
> Vgs threshold.

On closer inspection, I found the following values in the Power
Electronics book, referring to typical values for high voltage power
N-ch mosfets:

   Rds(on)   +0.7%/K  (fully enhanced D-S resistance)
   V(br)dss  +0.1%/k  (D-S breakdown voltage)
   Channel carrier mobility
             -0.6%/K
   Vgs(th)   -5mV/K   (G-S threshold, approx -0.25%/K)
   gfs       -0.2%/K  (transconductance)

Note that Rds(on) is not really a linear/exponential function as shown, but
averages out to this value over a range of 25-200 deg C.

All else being equal, a P-ch mosfet will have 2 to 3 times the Rds(on) of
an N-ch device.  Thus a 'complementary' pair will require 3 times the
drive to the P-ch device's gate capacitance, because of its larger required
area for same Rds(on).


>
> BTW, the bias stability probems I referred to was with an array of Siliconix
> VN88/AF devices; many years ago.  Despite many calls to the factory
> luminaries, I never did achieve satisfaction.  Bias was near impossible to
> stablize, adn current sharing was hap-hazzard.  I concluded that MOSFETS are
> fine for switching circuits, but despite the seeming advantages, not for
 linear.

The problem with running parallel mosfets is that drain current can have -ve
or +ve tempcos depending on Vgs.  There exists a certain value of Vgs where
the tempco is roughly zero.  Below this level of Vgs, the drain current can
in fact exhibit thermal runaway for constant Vgs.  Above this level,
overcurrent at low temperature can be a problem (but hopefully self-correcting).

This points to problems in paralleling mosfets for linear applications.  It
would be best to include source current-sharing resistance, and select
devices which are manufactured to have reasonably matched character i.e.
don't just use dirty great SMPS switches.

Regards,
SJH
Canberra, Australia