Because of the number of request from list members,
I'm posting this to the list.


External Hardware for I2C Start/Stop Detection
(This diagram contains some special characters which only
 makes sense in DOS)

                                     VCC
                                      A
                                      *
                                   UAAoAA(
                                   * PRN * '74HCT74'
       SCL  AAAAAAAAAAAAAAAAAAAAAAA*D   Q*
                         *         *     *
                         *         *    _*
       SDA  AAAAAAAAAA oAAAAAAAAAAA*CLK QAAAAAAAAAAAAAAAAAAAAA
IICINT
                   *     *         * CLRN*     *
                   *     *         AAAoAAU     *
                   *     *            *        *
                   *     AAAAAAA(     *        *
                   *     *      ANDAAAU        *
     RESET  AAAAAAAAAAAAAAAAAAAAU              *
                   *  *  *         '74HCT00'   *
                   *  AAAAAAAAAAAAAAAA(        *
                   *     *            *        *
                   *     *         UAAoAA(     *
                   *     *         * PRN *     *
                   *     AAAAAAAAAA*D   QAAAAAAAAAAAAAAAAAAAAA  STOP
                   *               *     *     *
                   *               *    _*     *
                   AAAAAAAAAAAAAAAA*CLK Q*     *
                                   * CLRN*     *
                                   AAAoAAU     *
                                      *        *
                                      AAAAAAAAAU


        ___       ____      ____       ____            _____
SDA        \_____/     ....     \_____/     .... _____/
        ______      __      _______      __       __________
SCL           \____/   ....        \____/   .... /
        ___    _________________    ________________________
IICINT     \__/                 \__/
        ___                                            _____
STOP       \__________________________________________/

            ^                    ^                     ^
            |                    |                     |
            +- Start             +- Repeated           +- Stop
               Condition            Start                 Condition
                                    Condition

Theory of operation

i.      Start condition detection
        - IICINT will exhibit a low pulse for length of around
          Thd:sta = 4.0us
        - this 4.0us low pulse is used to interrupt the
          microcontroller which within Thd:sta + Tlow = 8.7 us
          must be able to hold the SCL low to slow down the
          transfer rate.

ii.     As the SCL is held low by the slave, data transfer can
        proceed as dictated by the bit-banged slave.

iii.    Repeated start condition
        - This condition are used during Read/Write direction
          switch during the course of data transfer.
        - This generates another low pulse on IICINT as in (i)
          and should interrupt the bit-banged slave again, i.e.
          a "re-entrant" interrupt.
        - The "re-entrant" interrupt is the tricky bit, which
          with careful coding should be able to work.
          (Heck, it works with a 4-bit microcontroller!).

iv.     The STOP signal is used to detect when a transfer is
        taking place, so that a bit-banged master can roughly
        guess when it can jump on the bus.
        Can't implement a bit-banged master WITH arbitration
        yet.
        Anyway, as I know it the DURACELL's Smart Battery (SMBus
        @ I2C bus) implements the same method to get around
        bus arbitration.

As I mention earlier I do not have a PIC implementation,
so if anybody out there have successfully implement a
bit-banged slave for the PIC, it would be a courtesy
to share with others on the list.


Regards,

Peter Tiang
tiangcfoon@hitachi.com.my



 Transmit frame
                                          _
 [S][address][W](A)[Data](A).....[Data](A/A)[P]
  ^     ^     ^       ^   ^       ^
  |     |     |       |   |       |
  |     |     |       |   |       |
  |     |     |       |   |       +---- Stop Condition
  |     |     |       |   +---- Acknowledge = '0'
  |     |     |       +---- 8-bit Data (out)
  |     |     |       _
  |     |     +---- R/W = '0'
  |     +---- 7-bit Slave address
  +---- Start Condition

 [ ] = Master drive
 ( ) = Slave drive

 Receive frame
                                        _
 [S][address][R](A)(Data)[A].....(Data)[A][P]
  ^     ^     ^  ^    ^   ^             ^  ^
  |     |     |  |    |   |             |  |
  |     |     |  |    |   |             |  |
  |     |     |  |    |   |             |  +---- Stop Condition
  |     |     |  |    |   |             +---- Not Ack by Master = '1'
  |     |     |  |    |   +---- Ack by Master = '0'
  |     |     |  |    +---- 8-bit Data (in)
  |     |     |  +---- Ack by slave
  |     |     +---- R/W* = '1'
  |     +---- 7-bit Slave address
  +---- Start Condition

 [ ] = Master drive
 ( ) = Slave drive

 Combo frame (Transfer with change in direction)

  _

[S][address][W](A)[Data](A).....[Data](A)[Sr][address][R](A)(Data)[A].....(Data)
 [A][P]
                                           ^
                                           |
                                           +---- Repeated Start condition for ch
ange in
direction.
 [ ] = Master drive
 ( ) = Slave drive