On the contrary, a bit-banged I2C slave is possible to be
implemented.

What you need is a start condition detection circuit which
can be be implemented using cheap 74HCTxx logics.

If interested, please e-mail me.
And sorry, as I do not have the PIC codes.
I have a big-banged 100kHz slave on a 4-bit Hitachi's
microcontroller.


Regards,

Peter Tiang
tiangcfoon@hitachi.com.my

>> From: Mayes uk <mike@D-M-G.DEMON.CO.UK>
>>
>> Hi,
>>
>> I have looked around and found lots of code to implement
>> I2C master PICs, but I haven't found any code for
>> bit banging I2C slave.
>>
> Is there an ANxxx covering this?
> Has anyone got some code they could e-mail me, or pointer
> to some code?
>
>Is I mentioned in a previous post, the timing requirements
for
>the I2C
>slave even at 100KHz are too severe for a software
>implementation.
>This is why the 16CXX series implement a slave I2C in
>hardware, but
>leave the master implementation to software.

>The reason for this disparity is that the master drives the
>clock line,
>whereas the slave has to follow the clock and respond if
>necessary
>within quite tight timing constraints.

>This problem may be mitigated somewhat if you are writing
>both master
>and slave.  In this case, the master can be aware that the
>slave is
>slow and thus relax its clock rate to, say, 10KHz.  Strictly
>speaking,
>it is no longer an I2C slave, but may well be good enough for
>the
>application.

>Regards,
>SJH
>Canberra, Australia