In my former life, we did some more interesting things with caps in
     routing them to their respective ICs.

     Instead of tying a power/ground pin to the plane on a 4+ layer board,
     the via would have the normal pin clearance. On the surface where the
     cap is placed (usually the solder side for us), we'd have a thick
     trace (~20mil) from the pin to the respective pin of the bulk cap, AND
     THEN to a large via to the plane. This follows the theory of bypass
     where the cap is between the supply and the sink acting like a filter.

     Some caveats to this is that it is usually difficult to tie BOTH power
     pins (of, say, a 74AC00) to one cap under the chip. If you have a
     one-cap-per-IC philosophy, you have to decide whether to bypass power
     or ground by this scheme.

     This is also done to the (big) bulk caps where power enters the board:
     Run traces from the connector to the pads of the caps and then to the
     plane. Big traces. Also, we used 10-22UF in parallel with 0.1UF.

     Norm LeMieux
     MCHIP FAE/NW