Most of the multiplex LCD driver chips I've seen include a biasing network
to produce 1/3, 2/3, and full bias which are then used to drive the display;
the PIC 16C924 seems typical in that regard.

On a 3-way multiplexed display, blank pixels receive 1/3 voltage all the
time while dark pixels receive 1/3 voltage 2/3 of the time and full voltage
the other 1/3.

Is there any reason why this is done rather than using creative timing and
standard CMOS outputs?  Using a couple 74HC595s and some clever programming,
I have driven a 4.5 digit display (multiplexed 3x12) and found the contrast
to be quite good: excluding the time all pixels are off (PWM'ing for soft-
ware control of contrast), dark pixels are on 3/4 of the time while blank
pixels are on 1/4 of the time.

Note that on a 5:1 multiplex, the best timing will dark pixels on just over
2/3 of the time (and light pixels just under 1/3).  A 7:1 multiplex allows
dark pixels just under 2/3 and light pixels just over 1/3.  Note that the
programming for higher multiplexes gets increasingly complex; 3:1 is not too
hard, but 5:1 would be a pain and 7:1 would be a monster.  Don't even think
about 9:1 or 11:1.....