I'm currently in the development stage of a product using the pic 16c74 in PSP
 mode.
Here is my story, since the PSP mode uses RE0- RE2 for  CS, IOR, & IOW, and
 PORTB for the bi-directional data
implementing flowcontrol from the HOST processor is almost impossible with out
 the use of timming loops.
Unless you dedicate two more output pins for use as hardware flow control.

In my example,  202h is the PSP data port, and 203h(bit's 0 and 1) are for
 status.
Using this method I can achieve a 'Chipset' like interface with the PIC, as an
 example,
when talking with the a realtime-clock(RTC) cmos, you use 70h for the index, and
 71h for i/o.
I use 202h for index and data , and 203h for  Data Valid, and Write Mode.
Bit 0 being set when any output is sent to the PIC and acknowledge , with the
 result being placed in PORTB

My question is this. Is microchip(tm) planning on adding another CS ping to the
 pic, and stuffing another buffer in the part,
so i can do some REAL  index-offset addressing? It would sure speed things up.

I know other parts out there are doing this, but my hardware guys chose this
 part because of all its
features, which btw, I'm using 85% of :)

Thanks,
        Stephen