;8x51 version 1: 48 bits, 6us [assuming X is R1:R2 and Y is R3:R4]
            mov     A,R2
            add     A,R4
            mov     R2,A
            mov     A,R1
            addc    A,r3
            mov     R1,A
    ;8x51 version 2: 96 bits, 6us [assuming X and Y are in memory]
            mov     A,XL
            add     A,YL
            mov     A,XL
            mov     A,XH
            addc    A,YH
            mov     XH,A

Not to detract from your conclusions, but aren't you leaving out "effective
address fetch time" or something?  I have a hard time believing that any
processor can fetch twice as many bytes in its instruction stream and
maintain the same execution time...

BillW