Hello Jim!

05 Sep 96, PICLIST@MITVMA.MIT.EDU writes to Alexej Vladimirov:

 P> does anyone know what the nature of the corruption is, how long it
 P> lasts for and what causes it?

I forward my old message from the Microchip BBS.

=== Cut ===
Hello All!

I confirm PIC16C74 SCI hardware bug, described by:
Neilw(04-apr-95), Windels(28-jul-95), JScorse(29-jul-95) and
Dennis Millard(31-jul-95).

We use asynchronous 8-bit mode with following settings:

RCSTA=10010000, what means:         TXSTA=00100100, what means:
SPEN  - Serial port enable          CSRC  - Don't care
RC8/9 - Selects 8-bit reception     TX8/9 - Selects 8-bit transmission
SREN  - Don't care                  TXEN  - Transmit enabled
CREN  - Enables reception           SYNC  - Asynchronous mode
                                    BRGH  - High speed
                                    TXD8  - 9th bit of transmit data
We use Fosc=5 MHz and 9600 desired baud rate.
Calculated value for SPBRG at this conditions is 31.

At this conditions PIC receive with errors (mostly on bit7).
Errors is depended from settings bit SREN, which is defined "don't care".
If bit SREN=1, for codes from 40h to 7Fh, bit7 frequently sets to 1.
               for codes with bit0 set to 1, bit7 also sets to 1.
If bit SREN=0, random errors occurs.
Errors is also depended from SPBRG settings.
If decrease SPBRG value - 30 instead of 31 desired, error probability
decreases and errors from bit0 disappears. Other errors remains.

Test program (loop-back test):

list c=132,p=16c74,r=dec,t=on,x=on,e=1
title "SCI TEST Programm"
#include "p16cxxd.inc"
#include "p16cxx.inc"
; Definition
movlf macro Fil,Lit
 movlw Lit
 movwf Fil
 endm
;
U%mail.ormix.riga.lv
 org 0
 goto Start
;
U%mail.ormix.riga.lv
 org 4
 goto 0
;---------------------------------------------------------------
Start
 clrwdt
 bsf STATUS,RP0
 movlf (OPTION_REG&07fh),0ffh
 clrf (PIE1&07fh)
 clrf (PIE2&07fh)
 clrf INTCON
; Set Serial interface
 movlf (TXSTA&07fh),10100100b ;SCI 8 bit transmitt async /16
; movlf (SPBRG&07fh),30 ;9600 (10.080645161) Baud
 movlf (SPBRG&07fh),31 ;9600 (9.765625) Baud
 bcf STATUS,RP0
 movlf RCSTA,10110000b ;SCI enable 8 bit receive
Tloop
RxBt
; Wait while RxReg is empty
 btfss PIR1,RBFL
 goto RxBt
; Receive byte
 movfw RCREG
 btfss RCSTA,OERR
 goto TxBt
 bcf RCSTA,CREN
 bsf RCSTA,CREN
TxBt
; Wait while TxReg isn't empty
 btfss PIR1,TXIF
 goto TxBt
; Transmit byte
 movwf TXREG
 goto Tloop
;
U%mail.ormix.riga.lv
 end

Work-around:
At the same circuit we change BRGH=1 to BRGH=0.
Calculated value for SPBRG at this settings is 7.
All works fine.
We check also at 19200 bps (SPBRG=3) and at 38400 bps (SPBRG=1). No errors.

Summary: PIC16C74 SCI mode with BRGH=1 don't work.

We check this bug with PIC16C74/JW crystals with the following marking:
- PIC16C74 ENG SMP 9430 CAT Rev A2
- PIC16C74 ENG SMP 9502 CAT Rev A2
- PIC16C74/JW 9524 SAT
- PIC16C74ME A2 BOND 9443 CAA - Emulator pod

Crystal with the following marking work without this problem:
- PIC16C74/JW 9508 CAT

=== Cut ===

Alexej Vladimirov  avlad@mail.ormix.riga.lv
http://www.ormix.riga.lv/eng/mchip/mchip.htm
...more than 170 Microchip-related links now...
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