>Design criterion: simple and cheap over accuracy.

Noteing that the circuit is to ONLY do this function, and that expense is
the primary concern, a minimum of external hardware is indicated.

I would do the DAC with a R-2R resistor ladder on PORTB and sample the input
pulse on a PORTA input. A level translator (comparator) may be required to
translate the input pulse to CMOS voltage levels and thresholds.

DAC resolution would be as high as 8 bits with accuracy limited by the
precision and matching of the resistors, impedance of the load, and accuracy
of the VCC supply.

A 12 bit PIC could do this job easily with perhaps 12 resistors, 4
capacitors, a crystal, a power supply circuit (as required) and a diode or
zener for input protection. Output buffering or input level translation
would require additional hardware. The least expensive PIC (except for the
newest 8 pin versions) could be used.

A PWM based DAC was a possibility except for 2 factors: 1) PICs with PWM
output are relatively expensive and bit banging a PWM output on one without
degrades the pulse width sense accuracy due to increased software loading.
2) PWM outputs inherently introduce integration delays. The lower the PWM
clock rate (and consequently lower software loading) the higher the time
constant for a given noise level. A R-2R DAC requires a much lower
integration time as only power supply and crystal noise need be removed.

My 2 cents...

Regards, Dana Frank Raymond
dfr@icom.ca