> From: Mike Jones <mike@newjay.win-uk.net>
>
> Hello PIC experts,
>
> I have couple of simple questions, which I haven't seen covered in any
> data sheets:-
>
> 1) What ESD precautions should I take when designing PIC application
> circuits? Do I tie unused i/o pins to VSS (or VDD) via a resistor, or
> is it safe to leave the pins disconnected and rely on the on-chip ESD
> protection?

If you are leaving the pins as _inputs_, tie directly to VDD.  If the
power supply is a bit dodgy, use a 4K7 resistor.  Only one resistor may
be used for all unused pins.  If pins are left as _input_ open
circuits, they may just float at a value which causes excessive current
drain.  This is a no-no for battery powered circuits.  However, the
sensible thing to do (which avoids all these problems) is to define
unused pins as ouputs.  They may then be safely left open-circuit.

>
> 2) Should I think about putting rf bypass/decoupling capacitors on
> the power supply lines near the chip? If so, what sort of values
> should I use?
>

Yes.  Use a 0.1uF monolithic or ceramic cap, and place as close as
possible to the device's VSS and VDD pins.  Note that if using one of
the PIC devices with more than one VDD/VSS pin make sure there is a
power net connection to _all_ such pins.  E.g. the 16C74 has two each
of VDD and VSS.  I run a thick (50mil) trace directly between each pair
and put one of those 0.1uF monocaps right up against one side.  This
pretty much case-hardens it against ground bounce and other problems.

Regards,
SJH
Canberra, Australia