Help!

There seems to be several varieties of SPI bus protocol, is this possible?
Like, clocking data in or out on falling or rising edge?  Or, what is the
state of the clock line when idle?  If this is in a FAQ somewhere, please
steer me there.

Particulars: PIC16C73 and Ramtron FM25160.  It seems that we select clock
polarity CKP=1 to get the proper I/O, but that means the SCK line sits high
between operations, which violates what the FM25160 requires.  It appears
that when CHIPSELECT is asserted for the memory part, it discovers the high
state of the clock line as if it were the first rising edge, and then
everything is off by one bit timing from then on.  Ramtron suggests we stick
in a one-shot... we thought we were reducing parts count, not increasing it!
We've thought of fiddling with CKP ``on the fly'', or asserting the
CHIPSELECT just after starting the SPI operation, instead of just before,
but we haven't thought these through.

I guess there's a ``Motorola'' flavor of SPI protocol, vs. ``National
Semi'', or one of the above vs. ``the rest of the world'', so if anyone has
wrestled some oddball SPI part operation down to the ground, please let us
know.  TIA.

Peter F. Klammer, Racom Systems Inc.                   PKlammer@ACM.Org
6080 Greenwood Plaza Boulevard                            (303)773-7411
Englewood, CO  80111                                  FAX:(303)771-4708