John Payson <PICLIST@MITVMA.MIT.EDU> wrote:

> > 1.  If the PIC's Vdd line drops below the operational threshold
> > (3V or so), but DOESN"T fall below 0.7V, the PIC will latch up
> > when power is restored, and the watchdog timer will NOT reset it.
>
> By this, do you mean by the term "latchup", the "pseudo-SCR" latchup
> that hits CMOS devices when their substrate junctions get biased
> into conduction? If so, would using an LVI chip prevent it, or is it
> necessary to ensure that power dips are always taken down to zero?

John:

The "CMOS Latchup" problem you're describing DOES occasionally happen
(especially to the microprocessors on the PIC-Master emulator
probes), but it's unrelated to the specific problem I was discussing.

The "Brownout latchup" problem, as far as I know, is simply a symptom
of the PIC's logic circuitry starting to function at a lower voltage
than its RAM and EPROM circuitry.  Those Motorola/Ricoh/Maxim
low-voltage-reset chips solve the problem nicely.

-Andy

Andrew Warren - fastfwd@ix.netcom.com
Fast Forward Engineering, Vista, California
http://www.geocities.com/SiliconValley/2499