> 1.  If the PIC's Vdd line drops below the operational threshold (3V
> or so), but DOESN"T fall below 0.7V, the PIC will latch up when
> power is restored, and the watchdog timer will NOT reset it.

By this, do you mean by the term "latchup", the "pseudo-SCR" latchup that
hits CMOS devices when their substrate junctions get biased into conduction?
If so, would using an LVI chip prevent it, or is it necessary to ensure that
power dips are always taken down to zero?  I do know I once had a 16C84 chip
latch up on me (don't know why, but the chip was getting warm and drawing
150mA; powering the chip down and back again fixed it).