>>      Hello,
>>
>>      Working on a VHDL synthesizable model for the PIC (haven't pinned down
>> ......
>>So, what are the uses of the different clock phases
>
>Exactly what I've been looking for!
>
>I was thinking of synthesizing a PIC on an FPGA for In-Circuit Emulation
>but I don't have the time to do it.  You see, with such a core, we could
>add several debug features (similar to Motorola's BDM) and design a
>full-featured Emulator.
Fascinating!  I have had CORES on my brain 'cause of
a project here.  An ICE application never even occured to me.

>I agree with you.  Why have the different clock phases?
Absense of a generalized Memory, I/O Bus sure does simplify things!

The VHDL model would include the MEMORY data and address "ports", a clock
input "port" (this isn't SPICE; so I'm not modeling any analog phenomena),
and, of course, the RA, RB, RC ports.  Also, MCLR and RTCC.

Re the 1994 Microchip Databook; p2-7 tells me the rising edge of Q1 is pretty
central.  Starting on p2-8; looks like the RTCC is related to rising edge of
Q4.  p2-128 seems to say outputs on the ports are latched every Q1, and input
ports sampled every Q2.  Maybe, that is all I need...?...

Thomas.Coonan@Sciatl.com