>>     Working on a VHDL synthesizable model for the PIC (haven't pinned down
>>So, what are the uses of the different clock phases
>>
>>     tom coonan
>>     Thomas.Coonan@Sciatl.com
>
>Would you be up for Verilog? I find Verilog a bit easier/faster to
>code/understand.
Writing it in ViewLogic's VHDL.  Should be easy enough to port.  Since I want to
keep it perfectly synthesizable, no tricky coding styles.

>You can get the QuickLogic FPGA tools for $99. This is their full tool kit
>minus the programming software....
ViewLogic includes full VHDL simulation that isn't necessarily tied to synthesis
or any particular part.  I can write general VHDL test-benches, behavioral
models of RAMs, etc.  Very nice.

>Right now, they have 1k/2k/4k/7k/8k parts. By this time next year, they will be
>up to 20k gate parts.
It'll be interesting to see what my gate count and utilizations turn out to be.
Not quite ready to synthesize yet, though...