>     Hello,
>
>     Working on a VHDL synthesizable model for the PIC (haven't pinned down
>     any particular one yet..), partly for fun, perhaps for a future FPGA..
>     (BTW, is there demand for such a beast?  Let me know!).  The PIC
>     architecture is gloriously simple and to the point - making my job
>     straight forward.  So, what are the uses of the different clock phases
>     Q1, Q2, Q3 and Q4?  I see that Q1 latches the INSTRUCTION register.  I
>     also notice references to Q2 and the RTCC.  Is that it?  Any hints?
>
>     tom coonan
>     Thomas.Coonan@Sciatl.com

Would you be up for Verilog? I find Verilog a bit easier/faster to
code/understand.
Once in Verilog, you can run Veri2Vhdl to get into VHDL. I do not know of
any tools which go the other direction.

What tools do you have access to?

You can get the QuickLogic FPGA tools for $99. This is their full tool kit minus
the programming software. Their parts are full auto-place and auto-route with
generally 100% gate utilization (yes, 100% because they have so many routing
resources). The have Verilog synthesis in their package. Also, the parts come in
a variety of speed grades with the fastest being WICKED fast.

Right now, they have 1k/2k/4k/7k/8k parts. By this time next year, they will be
up to 20k gate parts.

cheers
eric