Hello,

     Working on a VHDL synthesizable model for the PIC (haven't pinned down
     any particular one yet..), partly for fun, perhaps for a future FPGA..
     (BTW, is there demand for such a beast?  Let me know!).  The PIC
     architecture is gloriously simple and to the point - making my job
     straight forward.  So, what are the uses of the different clock phases
     Q1, Q2, Q3 and Q4?  I see that Q1 latches the INSTRUCTION register.  I
     also notice references to Q2 and the RTCC.  Is that it?  Any hints?

     tom coonan
     Thomas.Coonan@Sciatl.com