> >What about CLRW?  Does
> >that read [IND] if the 7 lsb's of opcode are zero?  Would changing the 7
> >LSB's to something else cause that something else to be read [hopefully
> >harmlessly] instead?
>
> An interesting question, if it exists this side effect could be useful for
> something (not sure what yet).  If the possible extra read could be a
> problem, you could replace CLRW with ANDLW 0 (exactly the same effect as
> CLRW; W=0 and Z flag =1) or of course MOVLW 0 (W=0, but Z unchanged) instead
> and forget about the CLRW "instruction" (as you've noticed, it's actually
> coded as CLRF x,w) altogether.

I was just realizing that, because of the existence of writable registers
in the 16Cxx (though not 16C5x) which are altered by reading, MOVWF has to
be an oddball instruction; on the 16Cxx, almost all of the instructions whose
first two bits are "00" fit the following formula:
  read F-register selected by OP0-6
  take that and W; compute a value and flags [incl. "skip" flag] using the
    operation specified by OP8-12
  store the result in W if OP7 is 0, or back in the F resister if OP7 is 1

The only exceptions are:
  movwf
  nop
  clrwdt
  retfie
  return
  sleep
  tris
  option

Note that were it not for the existence of read-modified registers, even
these instructions could be executed with the above formula provided that
something else was "also" done [except for MOVWF, all of them would decode
as "take W and some F-register, then store W into W].  I wonder if that's
how they are in fact decoded on the 16C5x?

PS--Does anyone know how the TRIS and OPTION instructions are decoded?  I'd
like to be able to access EECTL and EEDATA without having to muss around
with bank-switching on the 16C84.