>I try to use a PIC16C84 and I get MICROCHIP documentation. There is something
>strange:
>
>  PortB can generate INTERRUPT when there is change on RB.4..7, the
>documentation said: these pins are sampled on the Q1 cycle of read.
>The new input is compared with old latched value in every instruction cycle.
>
>HOW IT IS possible an interrupt occurs if portB is latched only on a READ
>instruction ?

When the port is read by the program, the interrupt-compare latch is reset
to agree with the present state of the port inputs.  Thus the interrupt
condition goes away then until a pin changes (actually, I think the RBIF
flag needs to be manually reset as well).  In other words, the read resets
the compare function so a further change is required.  The sampling is done
on every instruction cycle.  If the sample doesn't agree with the latched
value (last value read), the RBIF flag is set, which causes an interrupt if
RBIE and GIE are also set.

>Does this means that it's neccessary to read PORTB every time to generate
>an interrupt ?

No.  It is only necessary to read port B once while the external hardware is
in the 'non-interrupt' state (this defines what the state is), then clear
RBIF, and set RBIE and GIE.  The next change of one of the B4-B7 pins will
generate an interrupt.  Before leaving the interrupt routine, be sure that
the port and the latch agree with each other (by doing a read) and the RBIF
is clear so another interrupt won't occur immediately.

>MICROCHIP Doc. said: PortB can generate instruction in SLEEP mode, HOW it
>is possible if portB is latched only on a read ?

The latch is one input of the compare, the pin state is the other.  The
value in the latch is held during sleep from the last value read while the
CPU was running.  The path from the pins through to the comparators is
apparently held open during sleep.

>Is it a mistake of the MICROCHIP doc. ?

The system as it is described in the doc seems to make sense to me, though
their description isn't real clear.  I'm not sure why the convoluted
implementation of latching twice, it seems that a one-cycle pipeline
(generating a pulse each time a pin were different from the last cycle)
would have worked just as well if the RBIF indeed has its own latch.

-Mike