In order to avoid "truncation" warnings from MPASM, I suggested
    that instructions like MOVWF TRISA be replaced by
    MOVWF TRISA ^ 0x80 ('^' is the exclusive-OR operator).

    Jeff D. Pipkins <pipkins@BANGATE.COMPAQ.COM> then suggested that
    MOVWF TRISA & 0x7F was preferable.

    I replied, explaining that XORing the register had a useful
    side-effect:  Any accidental application of the XOR to a page-0
    register would generate a warning.

    Dave Madden <dhm@VHEISSU.III.NET> must not have understood, because
    he wrote:

>[As] I understand it, Jeff is correct.
>
>Here's why:
>
>The whole point of XORing the high bit, or otherwise masking it out,
>is to avoid spurious assembler warnings.  Those warnings tell you
>*nothing* except that you've provided an operand that will be
>truncated in the instruction.  Warning or no, the code will operate as
>intended iff you've set the RP bits correctly.

    Right so far, Dave.

>The assembler can't check that [the RP bits are set correctly] for
>you, and the warning is of no use.  If you put the top-bit-clearing
>magic in a macro, then Jeff's method is clearly the better way -- if
>you used XOR, then you would have to use the macro for some cases and
>not for others, or write another macro for Page 0 registers.  If you
>write XOR out in each instruction that needs it, you've still only
>succeeded in keeping the assembler happy, at the cost of cluttering
>your source code.  The important point is that *none* of this has any
>bearing on whether the code is correct!
> ....
>There's no way for the assembler to tell you that you've made a
>mistake in the first place

    Here's where you start to miss the point.

    Because, as you say, the RP bits must be set correctly for accesses
    to page-1 registers, you ALREAADY write different code for page-0
    and page-1 registers:  Page-0 accesses aren't bracketed by BSF RP0
    and BCF RP0 instructions, while page-1 accesses are.

    Let's say that you've written a macro for page-1 register-accesses.
    If you use my method, a MOVWF macro will look like this:

        MOVWF1  MACRO   REG
                MOVWF   REG^080H
                ENDM

    Now let's say you want to set all the PORTA pins to output low.
    You'd do the following:

        PORTA   EQU     5
        TRISA   EQU     85
        #DEFINE RP0     STATUS,5

                MOVLW   0
                MOVWF   PORTA
                BSF     RP0
                MOVWF1  TRISA
                BCF     RP0

    In this case, everything'll work fine.

    Now, let's assume that you forget that PORTA is on page 0 and
    accidentally make this mistake:

                BSF     RP0
                MOVWF1  PORTA
                BCF     RP0

    What happens?

    The XOR in the macro SETS the high-bit of PORTA's address, sees
    that this value is too large to fit in the instruction, and
    generates a "Truncation" warning.

    Good thing, too, because (again, as you said) the code generated
    by a MOVWF 0x85 is exactly the same as that for a MOVWF 0x05.
    Because the RP0 bit is set, though, this "exactly the same" MOVWF
    would have written to the wrong page.

    If you'd shortsightedly used the "AND 0x7F" instead of my
    "XOR 0x80", the assembler would have generated no warnings when
    you mistakenly tried to write to a page-0 register after setting
    the RP0 flag.

    Now do you get it, Dave?

    -Andy

--
Andrew Warren - fastfwd@ix.netcom.com
Fast Forward Engineering, Vista, California