>
> On Tue, 14 Mar 1995, Andy Hill wrote:
>
> > Darwin Hawes <hawes@PHYSICS.UBC.CA> writes:
> > > On Fri, 10 Mar 1995, Andy Hill wrote:
> > > > If the problem is worse when the window is covered, I'd agree with
> > > > the "uninitialized register/port" crowd.
> > >
> > > That would have been my guess, except that the power consumption rises if
> > > I put on the cover on a running processor, so it is not an uninitialized
> > > port on power up.  The processor seems to function both with and without
> > > the cover.
> > >
> > OK, and you stated earlier that the power consumption rises over a
> > period of seconds after you cover the processor window.  Do you have
> > enough data to tell if the rise is linear or more of an exponential
> > (RC-time-constant) sort of progression?  Do you have any tri-state
> > busses that aren't being driven for long periods of time?  Any ports
> > that are in input-mode that aren't being driven or pulled-up?
>
> The rise seems to be non linear, but in the opposite sense as an RC time
> constant.  It starts slowly, then increases rapidly, then stops.  There
> were a few inputs that were not being driven, but changing these did not
> have any effect.  I tried the same experiment with another 56, and a
> brand new '61.  The other '56 worked better than the first, only rising
> to 0.1mA.  The '61 had low power consumption with or without light.  From
> this I would guess it was some sort of damage from the UV erasing that
> caused the problem.
>
>
 What we have here is the photovoltaic effect. Small but with CMOS it doesn't
take much. The chip is acting like a solar cell and appling a small but
significant charge in the gate of a lot of the transistors. Not much, but
enough for them to leak a little bit each. Multiply by god knows how many
thousands and it becomes significant. The delay is due to the input capcitance
of the gate, it's real small, but then again the chip is silicon just not
optimized for the effect. The reason it doesn't build up enough to send
you off into the weeds is that you basicly have a no load solar cell that
has a max voltage just high enough to be noticeable, i.e. it barely gets
you into the linear region, but it can't switch the other half of the totem
pole.