Answer to Eric Smith:

>>> I can't see how an extra latch would save more than one instruction cycle.
>> I don't se how it would save any instruction cycles ???
> Well, because you could store the next address and then wait for the write
> to be done, before starting the next one.
OK, I see what you mean. However saving one instruction cycle is not
the issue. With a 4Mhz xtal the PIC can execute approx 10000 instructions
in the time it takes to do an EEPROM erase/write cycle (10ms), so saving
one instruction won't make a big difference.

> ...  Otherwise why would you want to
> write the address register while a write was in progress?
I won't !  --- But a write to the address register might happen by
accident. An "accident" could for example be a program run-away, caused
by some external event: Noise, static discharge, power failure.

The reason that I pointed out this problem is that Microchip has done
a lot to ensure that such an error can not happen, i.e. an EEPROM write
can only be initiated by executing the following sequence of inst.:
  MOVLW  55h
  MOVWF  EECON2
  MOVLW  0AAh
  MOVWF  EECON2
  BSF    EECON1,WR
and the WRENN (Write enable) bit must have been set. And writes to
the EEDATA register is ignored during the erase/write cycle.
All this is done to prevent data loss/corruption. But all this
security can be bypassed by writing to the EEADR register during
an EEPROM erase/write cycle. That's the point - not whether an
instruction cycle can be saved or not.


Michael Brinks