> Something I came across today - mpstart will read fuses and ID
> locations from withon a .obj file, so there's no need to keep
> setting the fuses each time you load it up. The only problem is
> that to get mpalc to place data at $2000-2007 you need to use
> org beyond its defined limits so you get a fatal error for each
> word of data when assembling.
> Perhaps ASPIC copes with this OK?

Of course ASPIC supports this. The file DEMO.ZIP available on my BBS
(604-597-3479), Microchip's BBS and a few ftp sites shows how. Here is an
excerpt:

(From PICMACRO.ZIP)

...
       .switch PICDEVICE

        .case   1654
        .cpu    16c54
_RESVEC =       $01FF                   ;16c54
IDLOC = _RESVEC+1
FUSELOC = $FFF
        DEFSEG  REGS,  $00, $20         ;initial regs
        DEFSEG  CODE, $000,_RESVEC      ;Base code segment
        DEFSEG  RESET,_RESVEC,_RESVEC+1 ;Reset Vector
        DEFSEG ID,IDLOC,IDLOC+4        ;ID word segment
        DEFSEG FUSES,FUSELOC,FUSELOC+1  ;Config fuses

        .else

        .case   1655
        .cpu    16c55
_RESVEC =       $01FF                   ;16c55
IDLOC = _RESVEC+1
FUSELOC = $FFF
        DEFSEG  REGS,   $00, $20        ;initial regs
...
<code ommitted>


        .switch PICDEVICE
        .case 1654
        .case 1655
        .case 1656
        .case 1657
_CP     = %00001000             ;Code protect (0 = PROTECT)
_WDTE   = %00000100             ;WDT 0 = disable
_LPOSC  = 0                     ;LP Osc select
_XTOSC  = 1                     ;XT Osc select
_HSOSC  = 2                     ;HS Osc select
_RCOSC  = 3                     ;RC Osc select

        .else
        .case 1671
        .case 1684
_CP     = %00010000             ;Code protect (0 = PROTECT)
_PWRTE  = %00001000             ;Power up timer enable 0=disable
_WDTE   = %00000100             ;WDT 0 = disable
_LPOSC  = 0                     ;LP Osc select
_XTOSC  = 1                     ;XT Osc select
_HSOSC  = 2                     ;HS Osc select
_RCOSC  = 3                     ;RC Osc select
        .else
        .case 1742
_FPMM1  = %00010000             ;Extended Microcontroller (0 = CODE
PROTECT)
_FPMM2  = %01000000             ;Microcontroller mode (0 = CODE PROTECT)
_FPMM3  = %01010000             ;Microprocessor mode (0 = CODE PROTECT)
_FWDT1  = %00001100             ;WDT prescaler = 1  (0=disabled)
_FWDT64 = %00000100             ;WDT prescaler = 1
_FWDT256 = %00001000            ;WDT prescaler = 256
_LFOSC  = 0                     ;LP Osc select
_RCOSC  = 1                     ;RC Osc select
_XTOSC  = 2                     ;XT Osc select
_ECOSC  = 3                     ;EC Osc select (external clock)
        .endif

...
(From PLD.ASM  (the initial file))
;**********************************************************************
;*
;* Define PIC options and ID
;*
;**********************************************************************
        .if !clop_d             ;simulator won't tolerate fuses!

        SEG FUSES               ;Config fuse area

        .word _XTOSC|_CP|_PWRTE ;Mode: xt osc, no code protext, timer
enabled

        .if isdef( IDLOC )      ;if there is an ID area (ie. not 17C42)
         SEG ID
         .word  _year&$0f,_month,_day,_hour      ;set id number to compile
time
        .endif
        .endif
----------------------------
Note that the above code also generates a default id code as the compile
time
in BCD.

- Don Lekei